FIG. 7 shows prior art multi-chip array 300 in which a series of individual chips 302 are placed end to end on a single substrate 304. Improper spacing can occur at the joints between the chips, impacting operation of the chips. For example, for chips with ink ejectors, jet interpolation may be needed at chip boundaries, and for photosensitive chips, imaging at the joints may be impaired. In addition, extending multi-chip silicon based arrays presents precision problems and requires the use of costly equipment and operations. Further, the desired operation of the individual chips cannot be fully tested before the chips are placed in the array. Many such multi-chip arrays do not enable easy rework of defective chips and rework of a defective chip in an array often results in damage to adjacent chips.
FIG. 8 shows prior art arrangement 400 of a plurality of printheads 402 arranged in a staggered stitch shift configuration, rather than a butted configuration. The arrangement includes four sets of printheads for yellow, cyan, magenta, and black, respectively. The staggered configuration eliminates spacing problems at the ends of the printheads by overlapping the printheads in process direction P. However, the configuration requires larger amounts of space in the process direction for the multiple rows of modules. A typical width 404 for a printhead 402 is about three inches and a typical resolution for a printhead 402 is 600 spots per inch. In FIG. 8, printheads are assumed to be separated by one inch in t4he process direction. Thus, arrangement 400 provides full color printing capability of 600 spots per inch, but requires over 787 millimeters in the process direction.